library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity internalClock is
	port(clk50_in 		: in std_logic;
       clk_out    	: out std_logic);
end internalClock;


architecture Behavior of internalClock is
	signal clk : std_logic :='0';
begin
	
	process (clk50_in)
		
		variable cycles : integer := 1;
		begin
		
		if rising_edge(clk50_in) then
			
			if (cycles=50000000/100) then --30Hz
				cycles := 1;
				clk <= NOT(clk);
			end if;
			
			cycles := cycles+1;
			
		end if;
		
		clk_out <= clk;
	
	end process;

end architecture Behavior;